A method of inserting test points into semiconductor integrated circuits has been used as one means for testing semiconductor integrated circuits. Generally, there are three kinds of test points: a “1” control point which increases the controllability of signal lines to “1” (hereinafter called “1” controllability), a “O” control point which increases the controllability of signal lines to “O” (hereinafter called “O” controllability), and an observation point which increases the observability of a signal value of a signal line. The “1” and “O” control points are simply called control points when they need not be distinguished from each other.
Methods of analyzing circuits and locations of such test points are disclosed in “Test Points Insertion for Scan-Based BIST (Built-In Self Test)” by B. Seiss and others (P.253 through 262), “Proceeding of 2nd European Test Conference (1991) and “Circuit having improved testability and Methods of improving testability of circuits,” Japanese Non-examined Patent Publication No.06-331709 (1994).
Particularly, the test point analyzing method in the former document determines each test point to minimize a cost function which is defined by a probability-based testability scale called COP (Controllability observability Procedure). In other words, a procedure to determine one test point comprises selecting approximate test point locations according to estimated values of the cost function for insertion of test points, calculating an actual value of the cost function for insertion of the test point on each possible location, selecting a location which minimizes the cost function, and placing the test point there. This procedure is repeated until all test point locations are determined. From experiments, it is recognized that this test point analyzing method is effective for testability of random-number patterns.
Further, some methods have been provided to reduce the area overhead due to provision of test points. One of such methods is disclosed in “Testability designing for attaining a complete detection ratio,” Design Automation Research Document 19 (1983), Information Processing Society of Japan. In this document, the number of controllable elements can be reduced by controlling a plurality of control points having a single common output element by branching from one controllable element. Another method is disclosed in “Modifying user Defined Logic for Test Access to Embedded Cores” by B. Pouya and others (P.60 through 68), “Proceeding of International Test Conference” (1997). It proposes sharing test data input lines of control points.
This method performs an implication operation from a control point location toward the input and shares pairs of signal lines which input test data to control points causing no redundant fault even when they are shared.
Another technology for testability of semiconductor integrated circuits is a scanning method wherein a circuit is added which enables the setting of values for all flip-flops (hereinafter abbreviated as FFs) and provides for reading values from them. This scanning method can treat a sequence circuit having an internal status which makes generation of a test pattern difficult as a combination circuit having no internal status. The scanning method can be loosely divided into two methods: a shift-scanning method which uses shift registers to set values in chain-connected FFs and which reads values from the FFs, and an address scanning method which uses addresses assigned to FFs to select a FF to set a value or to read a value from it. In general, the shift scanning method uses a simpler circuit than the address scanning method. However, the address scanning method can select FFs more easily to set values or to read values from them.
However, the shift scanning method accesses all FFs that are chain-connected (hereinafter called a scan chain) even when part of the scan chain is value-set or read because the FFs work as shift registers. Therefore, the problems of the shift scanning method are to provide the ability to handle a great quantity of data required for testing (quantity of test data) and to take much time to effect the test. A technique for solving these problems is disclosed in “Semiconductor Integrated Circuit,” Japanese Non-examined Patent Publication No.09-5403 (1997). This technique comprises dividing flip-flops (FFs) in the scan chain into a plurality of groups and placing a by-path selector on each dividing point to selectively bypass respective FF groups and disabling the FFs belonging to the bypassed groups.
This technique reduces the number of steps to set values to flip-flops and consequently reduces the quantity of test data and the time required for testing.